13:45–15:30
South Hall 2 B (Floor 2)
Hardware Testing: Bringing Hardware-in-the-Loop to Zephyr CI
Parthiban N
Linumiz
With more than 1,000 supported boards, no developer can test every configuration, and emulators alone miss silicon edge cases: changes that pass CI get reverted weeks later. This maintainers' forum session sets out to decide whether Zephyr wants hardware-in-the-loop testing in CI and, if so, how board tiers, lab hosting and result reporting on PRs should work.
Co-hosted with
- DK Dan Kalowsky · Qualcomm · Lead organizer & moderator
What you'll learnHide
- D1–D2: HIL in CI/CD, and reviving the hardware tier system
- D3–D4: what each tier covers, and how tiers are identified in-tree
- D5: where HIL boards are hosted
- D6: scheduler framework (LabGrid, LAVA, agnostic or hybrid)